1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, and particularly to a structure of a signal input/output unit providing an interface between this semiconductor integrated circuit device and an external device. More particularly, the present invention relates to a structure of a signal (including data signal) input/output unit of a synchronous semiconductor memory device that operates in synchronization with a clock signal.
2. Description of the Background Art
FIG. 15 schematically shows an entire structure of a conventional synchronous semiconductor memory device. Referring to FIG. 15, a synchronous semiconductor memory device 1 includes an input circuit 2 operating with a power supply voltage Vddi applied to a power supply node 1a or a power supply voltage Vdd from a power supply node 1d and a ground voltage Vss as both operating power supply voltages for taking in an externally applied input signal IN at an input node 1c in synchronization with a clock signal CLK applied from a clock input node 1b, to generate an internal signal of a power supply voltage Vdd level, a memory internal circuit 3 operating with a power supply voltage Vdd applied to power supply node 1d and ground voltage Vss applied to a ground node 1e as both operating power supply voltages for carrying out a memory cell select operation and data writing/reading operation according to a signal applied from input signal 2 in synchronization with clock signal CLK, and an output circuit 4 operating with a power supply voltage VddQ applied to a power supply node 1f and a ground voltage VssQ applied to a ground node 11 as both operating power supply voltages for providing memory cell data read out from memory internal circuit 3 to a data output node 1h.
Power supply voltage Vddi is at a level according to the power supply voltage level of the system in which synchronous semiconductor memory device 1 is employed. For example, power supply voltage Vddi takes the level of 2.5V or 1.8V. Power supply voltage Vdd is the power supply voltage used for the internal operation of synchronous semiconductor memory device 1. Power supply voltage Vdd is higher than power supply voltage Vddi, and is, for example, 3.3V. By using power supply voltage Vddi as one operating power supply voltage in input circuit 2, the input logic level of the memory device is adapted to the interface of a separate logic or processor and to the power supply voltage level of the system in which this synchronous semiconductor memory device is employed.
Input signal IN applied to input circuit 2 includes an address signal, a control signal, and write data. Memory internal circuit 3 includes a memory cell array with a plurality of memory cells, and a data write circuit and data read out circuit performing data writing and reading in synchronization with a clock signal.
Power supply voltage VddQ and ground voltage VssQ dedicated for output are applied to output circuit 4. Output node 1h has a width of a plurality of bits such as 16 bits to allow many output buffers in output circuit 4 to operate simultaneously due to the dedicated voltages VddQ and VssQ. Output circuit 4 has to drive a large output load. This large output load must be driven at a high speed. By applying power supply voltage VddQ and ground voltage VssQ exclusively for data output, output circuit 4 can be operated stably. Also, the adverse effect of the power supply noise during operation of output circuit 4 on the operation of other circuits can be prevented.
Input circuit 2 receives a voltage Vddi according to the system power supply voltage as one operating power supply voltage to the first stage thereof connected to input node 1c, and takes in a signal according to this external interface to alter the voltage level for generating an internal signal of a power supply voltage Vdd level.
Ground voltage Vss to input circuit 2 may be applied via a node dedicated to the input circuit or via ground node 1e.
FIG. 16 shows an example of a structure of the first stage of input circuit 2 of FIG. 15. Referring to FIG. 16, the first stage of the input circuit includes a buffer circuit 2a operating with power supply voltage Vddi as one operating power supply voltage, and rendered operative when a first input stage cut signal ZNC generated from internal circuitry not shown is inactive (H level:logical high) for buffering an externally applied input signal IN for transmission to a node A, an inverter circuit 2b operating with power supply voltage Vddi as one operating power supply voltage for inverting the signal transmitted to node A from buffer circuit 2a, a level converter 2c for converting the amplitude of a signal applied to a node B from inverter circuit 2b to a level of power supply voltage Vdd, and an inverter buffer 2d operating with power supply voltage Vdd as one operating power supply voltage for buffering a level converted signal output from level converter 2c to generate an internal signal INT onto a node E.
First input stage cut signal ZNC applied to buffer circuit 2a is generated according to, for example, a chip select signal and a clock signal CLK. When first input state cut signal ZNC attains an active state of an L level (logical low), the synchronous semiconductor memory device attains a stand-by state. Therefore, no access is effected.
Buffer circuit 2a includes a p channel MOS transistor 2aa connected between a power supply voltage Vddi supply node Vddi (the node and the power supply voltage applied thereto are indicated by the same reference character hereinafter) and node A, and receiving first input stage cut signal ZNC at its gate, a p channel MOS transistor 2ab connected between power supply node Vddi and node A, and receiving an input signal IN1 at its gate, and n channel MOS transistors 2ac and 2ad connected in series between node A and a ground voltage Vss supply node (referred to as ground node Vss hereinafter). First input stage cut signal ZNC is applied to the gate of MOS transistor 2ac. Input signal IN1 is applied to the gate of MOS transistor 2ad.
Inverter circuit 2b includes a p channel MOS transistor 2ba connected between power supply node Vddi and node B, and having a gate connected to node A, and an n channel MOS transistor 2bb connected between node B and the ground node, and having a gate connected to node A. Inverter circuit 2b has a structure of a CMOS inverter.
Level converter 2c includes a p channel MOS transistor 2cc connected between power supply node Vdd to which power supply voltage Vdd is supplied and a node C, and having a gate connected to a node D, a p channel MOS transistor 2cd connected between power supply node Vdd and node D, and having a gate connected to node C, an n channel MOS transistor 2ca connected between node C and the ground node, and having a gate connected to node B, and an n channel MOS transistor 2cd connected between node D and the ground node, and having a gate connected to node A. This level converter 2c has a structure of a shift latch type level converter.
Inverter buffer 2d includes a p channel MOS transistor 2da connected between power supply node Vdd and a node E, and having a gate connected to node C, and an n channel MOS transistor 2db connected between node E and the ground node, and having a gate connected to node C. Internal signal INT on node E is incorporated into the input circuit shown in FIG. 15 in synchronization with clock signal CLK. Internal signal INT is also used for the internal operation.
The operation of the first stage of the input circuit of FIG. 16 will be described hereinafter with reference to the operation waveform shown in FIG. 17.
Before time t0, first input stage cut signal ZNC is at an active state of an L level. In buffer circuit 2a, MOS transistors 2aa and 2ac is in a conductive state and a non-conductive state, respectively. Therefore, node A is charged to the level of power supply voltage Vddi by MOS transistor 2aa irrespective of the voltage level of input signal IN1. Inverter circuit 2b inverts the signal of node A. Also, level converter 2c inverts the logic level of node B to transmit the inverted signal to node C (level conversion is carried out). Inverter buffer 2d inverts the logic level of node C for transmission to node E to generate internal signal INT. Thus, prior to time t0, nodes A, B, C and E have voltage levels of an H level, an L level, an H level, and an L level, respectively.
At time t0, first input stage cut signal ZNC rises to an H level of an inactive state. In response, MOS transistors 2aa and 2ac are rendered nonconductive and conductive, respectively, whereby buffer 2a which is the first stage of the input circuit operates as a CMOS inverter. At time t1, input signal IN1 is driven to an H level, whereby node A is discharged to the level of ground voltage Vss via MOS transistors 2ac and 2ad. In response to a low voltage level of node A, MOS transistor 2ba in inverter circuit 2b is rendered conductive, whereby the voltage of node B is driven from an L level to an H level (the level of power supply voltage Vddi).
In level converter 2c, MOS transistor 2ca is rendered conductive according to a raised voltage of node B, whereby node C is discharged to the level of the ground voltage. In response, MOS transistor 2cd conducts to increase the voltage level of node D. In response, MOS transistor 2cc makes a transition to a non-conductive state. MOS transistor 2cb attains a non-conductive state since the voltage of node A attains an L level. MOS transistor 2ca reduces the voltage of node C to the level of the ground potential. In response, the conductance of MOS transistor 2cd is increased to charge node D at a higher speed. Eventually, node C attains the level of the ground voltage, and node D attains the level of power supply voltage Vdd.
In response to this voltage reduction at node C, the voltage level of internal signal INT applied to node E from inverter buffer 2d is driven to an H level (the level of power supply voltage Vdd) from an L level.
At time t2, input signal IN1 is pulled down from an H level to an L level. In buffer circuit 2a of the first stage of the input circuit, MOS transistors 2ab and 2ad are rendered conductive and non-conductive, respectively, whereby the voltage of node A rises to the level of power supply voltage Vddi. When the voltage level of node A becomes higher than the input logic threshold value of inverter circuit 2b, the voltage of node B begins to drop and to be discharged to the level of the ground potential. In response, MOS transistors 2ca and 2cb are driven to a non-conductive state and a conductive state, respectively, in level converter 2c. As a result, the voltage of node D is reduced. MOS transistor 2cc conducts to charge node C. Accordingly, the voltage of node C rises to the level of power supply voltage Vdd, and the voltage of node D falls to the level of the ground voltage. The voltage level of node C is inverted by inverter buffer 2d, whereby internal signal INT on node E is lowered to the ground voltage level.
At time t3 when input signal IN1 is driven again to an H level from an L level, an operation similar to that at time t1 occurs. The voltage of node A is pulled down from an H level to an L level, and the voltage of node B is pulled up to an H level from an L level. In response, the voltage of node C is pulled down from an H level to an L level. Then, the voltage of node E is pulled up from an L level to an H level.
As shown in FIG. 16, a power supply voltage Vddi of a level identical to that of the power supply voltage of the system is applied as one operating power supply voltage to the first stage of the input circuit connected to the input node and serving as an interface. The logic amplitude of externally applied input signal IN1 can be identified correctly to generate an internal signal according to the logic level of this input signal IN1. In order to operate the internal circuit at high speed, the voltage level is converted to power supply voltage Vdd higher in level than power supply voltage Vddi by level converter 2c. Then, the output signal of level converter 2c is amplified by inverter buffer 2d to generate internal signal INT speedily with a relatively greater driving capability.
By the series of operations, an internal signal INT of a logic level according to input signal IN1 can be generated precisely and speedily to carry out an internal operation even when the logic amplitude of input signal IN1 differs from the logic amplitude of internal signal INT. Internal signal INT is incorporated in synchronization with clock signal CLK to be subject to a required process.
FIG. 18 shows an example of a structure of the last stage of output circuit 4 shown in FIG. 15. Referring to FIG. 18, output circuit 4 includes an inverter 4a receiving an internal read data /RD, an NOR circuit 4b receiving an internal read data /RD and an output enable signal /OE, a NOR circuit 4c receiving an output signal of inverter 4a and output enable signal /OE, an inverter circuit 4d receiving an output signal of NOR circuit 4b, an n channel MOS transistor 4e connected between a node supplying power supply voltage VddQ (referred to as power supply node VddQ hereinafter) and an output node J, and receiving an output signal of NOR circuit 4b at a gate thereof, an n channel MOS transistor 4f connected between output node J and the node that supplies ground voltage VssQ (referred to as ground node VssQ hereinafter), and receiving an output signal of NOR circuit 4c at a gate thereof, and a p channel MOS transistor 4g connected between power supply node VddQ and output node J, and receiving an output signal of inverter 4d at a gate thereof. The one operating power supply voltage of inverter circuits 4a and 4d and NOR circuits 4b and 4c may be internal power supply voltage Vdd or may be power supply voltage VddQ. The operation of the output circuit shown in FIG. 18 will now be described with reference to the signal waveform diagram of FIG. 19.
Before time t0, output enable signal /OE is at an inactive state of an H level. The voltages of output nodes G and NH of NOR circuits 4b and 4c is at an L level. Therefore, MOS transistors 4e and 4f are both kept non-conductive. Also, the output signal of inverter 4d is at an H level, and p channel MOS transistor 4g is in a non-conductive state. Therefore, output circuit 4 is in an output high impedance state.
At time t0, output enable signal /OE attains an active state of an L level, whereby output circuit 4 is rendered operative. In this state, NOR circuits 4b and 4c operate as inverters. When internal read data /RD read out from a memory cell attains an H level, NOR circuit 4b provides an output signal of an L level and NOR circuit 4c provides an output signal of an H level. Therefore, MOS transistors 4e and 4g are rendered non-conductive, whereas MOS transistor 4f is rendered conductive. Node A is discharged to the level of ground voltage VssQ.
When internal read data /RD is pulled down to an L level from an H level at time t1, the output signal of NOR circuit 4b is driven to an H level. MOS transistors 4e and 4g are rendered conductive. NOR circuit 4c provides an output signal of an L level, and an MOS transistor 4f is rendered non-conductive. Therefore, output node J is driven to the voltage level of power supply voltage VddQ by MOS transistors 4e and 4g.
At time t2, when internal read data /RD is pulled up to an H level from an L level, the voltage of output node E of NOR circuit 4b is pulled down to an L level from an H level. MOS transistors 4e and 4g are rendered non-conductive. The voltage of output node NH of NOR circuit 4c attains an H level, whereby MOS transistor 4f conducts. Output node J is discharged to the level of ground voltage VssQ.
The reason why n channel MOS transistor 4e and p channel MOS transistor 4g are employed to raise the voltage level of output node J to power supply voltage VddQ is described in the following. When the voltage level of node G rises only of the level of power supply voltage VddQ, n channel MOs transistor 4e cannot drive output node J to the voltage level of power supply voltage VddQ (threshold voltage loss). This loss of the threshold voltage of MOS transistor 4e is replenished by p channel MOS transistor 4g driving output node J to the level of power supply voltage VddQ. As a result, the voltage at output node J exhibits a full swing between power supply voltage VddQ and ground voltage VssQ.
A semiconductor memory device is employed in various systems. As a system power supply voltage thereof, various voltage levels such as 2.5V, 1.86V, or a lower voltage are used. If interface circuits (input/output circuits) optimized corresponding to the interfaces of various voltage levels are to be produced, the number of types of synchronous semiconductor memory devices increases. The product management will become tedious. In addition, when the system power supply voltage is altered, there will be no compatibility in the synchronous semiconductor memory devices. This is not economic for the user. If power supply voltages of a plurality of interface levels can be accommodated with one chip, the product management can be simplified, and it also becomes more convenient for a user to use the memory devices. However, problems as set forth in the following arise when the power supply voltage is converted with a structure of the first stage of input circuit using MOS transistors as shown in FIG. 16. The current driving capability of a MOS transistor varies according to the gate voltage thereof. The current driving capability becomes greater as the gate voltage becomes higher (square characteristics in saturated region).
Referring to FIG. 20, a case is considered where a circuit is implemented satisfying required conditions with a power supply voltage Vddi of 2.5V, for example. When input signal IN1 is driven to an L level from an H level, node A is charged to the level of power supply voltage Vddi by MOS transistor 2ab. In response to this voltage rise of node A, the potential of node B is reduced. The voltage amplitude of nodes A and B corresponds to the power supply voltage Vddi level. When the voltage of node A is raised, the conductance of MOS transistor 2cb is increased, whereby the voltage of node D is reduced to the ground voltage level. Then, node C is charged to the level of power supply voltage Vdd via MOS transistor 2cc.
When MOS transistor 2cc conducts, the voltage of node D is discharged to the level of the ground voltage. Therefore, MOS transistor 2cc charges node C to the level of power supply voltage Vdd without an effect of power supply voltage Vddi. MOS transistor 2ca drives node B to the ground voltage level when rendered non-conductive. The voltage level of node C is inverted by inverter buffer 2d, whereby the voltage of internal signal INT of node E is pulled down from an H level to an L level. Taking into account the delay time of each gate, the delay time of the transition of input signal IN1 to internal signal INT is assumed to be td.
When input signal IN1 is driven to an H level from an L level, node A is discharged by MOS transistors 2ac and 2ad to the level of the ground voltage. In response, the voltage of node B reaches the level of power supply voltage Vddi. The conductance of MOS transistor 2ca is increased, and the voltage of node C is reduced. In response to the reduction of the voltage at node C, MOS transistor 2cd is driven to a conductive state and MOS transistor 2cc to a non-conductive state. In response, the voltage of node C is driven to an L level, and internal signal INT is pulled up to the level of power supply voltage Vdd. In this case, the discharge rate of node C by MOS transistor 2ca is equal to the discharge rate of node D by MOS transistor 2cb. Accordingly, the charging/discharging rate of node C is considered to be equal. Therefore, the delay time of internal signal INT when input signal IN1 is driven to an H level from an L level is also td.
Consider the case where power supply voltage Vddi is set lower than 2.5V, i.e. set to 1.8V, for example. In buffer circuit 2a and inverter circuit 2b, the charge/discharge rate of nodes A and B is identical. However, the signal potential transition is slower than that in the case where power supply voltage Vddi is 2.5V since the current driving capability of the MOS transistor is smaller, as shown by the broken line in FIG. 20. Therefore, the delay time is increased.
When the voltage of node B attains the ground voltage level, MOS transistor 2ca attains a non-conductive state and MOS transistor 2cb attains a conductive state. In this case, the decrease in potential of node D is slightly more gentle than that in the case of 2.5V. However, node D is eventually discharged to the level of the ground voltage, so that MOS transistor 2cc drives node C to the level of power supply voltage Vdd at a charging rate faster than the discharging rate of MOS transistor 2ca. Therefore, the period of falling time of the voltage of node C becomes longer than period of rising time as shown by the broken line in FIG. 20. Accordingly, the rising time of internal signal INT of node E becomes longer to cause a slower rising rate.
When this power supply voltage Vddi attains a lower level such as 1.8V, the delay time of internal signal INT with respect to input signal IN1 includes a delay time td1 at the falling edge and td2 at the rising edge as shown in FIG. 20. The delay time of internal signal INT differs in the rising thereof and in the falling thereof from each other.
When internal signal INT has an amplitude of power supply voltage Vdd with a lower power supply voltage Vddi as shown in FIG. 21, the period of time required for internal signal INT to be driven to an L level from an H level differs from the period of time required for internal signal INT to be driven to an H level from an L level. More specifically, the time required for internal signal INT to be definite at H level differs from the time for internal signal INT to be definite at L level. Since the internal operation timing is determined by this worst case, the operating speed is determined by the rising time of internal signal INT. As a result, a high speed operation cannot be carried out. Particularly in the case where the rising and falling time of internal signal INT differs from each other, problems set forth in the following occur in a synchronous semiconductor memory device.
Referring to FIG. 22A, a synchronous semiconductor memory device has a set up time ts and a hold time th of signal INT determined with respect to a rise, for example, of clock signal CLK. When internal signal INT is set to L level for an active state thereof, the hold time th of internal signal INT becomes unnecessarily longer. Thus, transition to a subsequent operation cannot be effected speedily.
Referring to FIG. 22B, when internal signal INT is set to an H level to be activated at the rising edge of clock signal CLK, the set up time ts is shifted in the direction of the rise point of clock signal CLK. Therefore, the set up time ts becomes shorter to prevent proper incorporation of a signal.
In a general synchronous semiconductor memory device, the specification requires that the set up time ts is 1.5 ns and the hold time th is 0.5 ns when the clock signal CLK is 100 MHz. An intended operation cannot be reliably carried out unless internal signal INT is properly maintained at the level of a predetermined voltage during the set up time and the hold time. A proper operation cannot be guaranteed when the rising time and falling time of the signal varies to be different from the specification values of the set up time and hold time. When the timing offset is, for example, 0.2 ns, such offset value is greater than at least 10% of the permissible time of the set up time and hold time, and therefore when the specification value of the set up/hold time is determined taking into account such a large timing offset, high speed access cannot be realized.
In contrast, when the discharging rate and the charging rate of node C in level converter 3 is set to be equal with a power supply voltage Vddi of 1.8V, the discharging rate of node C becomes higher when power supply voltage Vdd takes a higher value of 2.5V. The rising time of internal signal INT becomes shorter to result in an opposite problem.
When power supply voltage VddQ in output circuit 4 of FIG. 18 is set to a voltage level identical to power supply Vddi in order to cooperate with an external interface, the charging rate of p channel MOS transistor 4g is reduced as the power supply voltage VddQ is lowered, and becomes slower than the discharging rate of the node J. If the charging and discharging rates of node A are set to be equal for a lower level of power supply voltage VddQ, the current driving capability of p channel MOS transistor 4g will become greater to result in a faster charging rate when power supply voltage VddQ becomes higher. In this case, ringing will occur at output node J by the greater current driving capability as shown in FIG. 23B. Some time is required until that ringing is dissipated. Therefore, data cannot be output speedily. In other words, the output data ascertion timing is delayed until the ringing is eliminated.
Further even if the voltage level of power supply voltage VddQ is constant, the load connected to output node J differs depending on the system in which the synchronous semiconductor memory device is used. When a synchronous semiconductor memory device is incorporated into a system by being arranged on a circuit board, the load capacitance of the wiring on the board differs for different systems, and the load of output node J will differ from system to system. If the load is small, the output node will be charged/discharged at high speed. This means that ringing will easily occur at output node J. Therefore, data cannot be output stably. Ringing occurs since a great load, particularly an inductance component, is present at, for example, the pad, the pin terminal, and the wires on the board. When a large load is present, output node J cannot be charged/discharged speedily, data cannot be set at an ascertained state at the rise of a clock signal as shown in FIG. 23, and erroneous operation will occur.
The above-described problems in an input/output circuit is encountered also in a general semiconductor integrated circuit device, not limited to a synchronous semiconductor memory device.